1. Field of the Invention
The invention relates generally to a monolithically intergratable storage circuit with storage cells which comprise cross coupled bipolar transistors and addressing elements for storage selection coupled to said bipolar transistors.
2. Description of the Prior Art
In electronic data processing systems binary coded data which has been received from logic circuits, or which is to be processed, as input data, or intermediate or final results has to be continuously stored. Storage devices, for example, tape and disk storages, offer a high storage capacity, but demand a relatively high access time. Thus there is need for high speed storage of medium capacity with comparatively low access time. These high speed storage arrangements can be realized with bistable or capacitively storing electronic circuits. Of the technically possible circuits the monolithically integratable semiconductor circuits are at present particularly attractive, economical factors being not the least important reason. For static storage cells formed in this technology flipflops are particularly used and can maintain their storage contents until altered through a writing process. Semiconductor technology permits the monolithic integration of comprehensive storage circuits or matrices by forming on a common semiconductor chip a multitude of such flipflops geometrically arranged in rows and columns. For the selection of the individual storage cells the semiconductor chips additionally contain the necessary logic circuits, e.g. decoders.
Static flipflop storage cells have already been developed in many versions in accordance with the predominant points of view as capacity, access time, power dissipation, packing density, manufacturing process, etc. Flipflop storage cells which are structured exclusively with bipolar or field effect transistors of a uniform or mutually complementary conductivity type also exist. Furthermore, hybrid storage cells with for instance bipolar transistors as flipflop transistors and field effect transistors as the load element, and vice versa are also known. All these versions have advantages and disadvantages, for instance, storage cells structured with complementary transistors have a very low power dissipation, but they involve a relatively complex manufacturing process. The present invention in particular relates to storage circuits whose basic circuits are flipflops with bipolar transistors. Particularly with respect to the storage circuits structured with unipolar or field effect transistors, respectively, the following points of view are decisive in the present case.
As already pointed out above, a storage system can be characterized by its capacity (quantity of contents) and its access time (delivery). The quotient of both factors is an indication for the quality of the storage. If only the storage cells themselves are considered, there actually exist many factors in favor of designing such semiconductor storages with field effect transistors for, with respect to bipolar transistors, they offer a higher packing density with a generally lower permanent power dissipation. However, logic circuits also have to be provided in large members in such a data processing system and here bipolar transistor circuits offer clearly superior properties compared with field effect transistor circuits, particularly with respect to their switching speed. Although the storage cells and the logic circuits can be separately assembled, there are limitations with respect to the number of the external connections that can be made between a semiconductor chip containing storage cells and the logic circuits required for decoding the storage cells. In a storage matrix with 2.sup.n rows and 2.sup.m columns which consequently contains 2.sup.n.sup.+m storage cells 2.sup.n word lines and 2.sup.m bit line pairs have to be provided for the selection of a storage cell. It is obvious that the selection of word and bit in modern day packing densities can no longer take place directly from the outside as the storage matrix would then require 2.sup.n + 2.sup.m external connections at the semiconductor chip. For a matrix of 512 = 2.sup.4.sup.+5 storage cells that would be 2.sup.4 + 2.sup.5 = 48 connections. The storage capacity per semiconductor chip selected for this example is easily obtainable by means of the manufacturing processes available today, and it is by no means an extreme example. If in the given example, however, the decoder circuits are provided on the semiconductor chip only 4 + 5 = 9 connections are required. Consequently, this shows that with the packing densities obtainable today require the selection circuits to be integrated on the semiconductor chip.
The access time of the respective storage circuit, however, depends not only the access time of the storage cells per se, but also substantially depends on the speed of the selection circuits. For that reason it is the general object of the invention to present a storage circuit with a short access time which offers the advantage of the speed of the bipolar transistors, and which can be realized in a manufacturing process adapted to the making of bipolar transistors, respectively.
A survey of the various known bipolar storage cells reveals that the word line is always connected to the two active flipflop transistors, see e.g. the book "Schaltkreistechnologien fur digital Rechenanlagen", by U. Baitinger, published by Wafter de Gruyter, 1973, pp. 219 to 221, and Elektronics, March 7, 1974, pp. 130 to 133, particularly FIG. 5 on p. 132. A disadvantage of such a coupling of the word line to the active flipflop transistors, however, is that upon selection, i.e. when the potential of the word line is decreased, the two cell nodes also decrease with respect to their potential, and that subsequently to the selection phase, i.e. when the potential of the word line increases again, they have to be recharged which involves a relatively high amount of time or demands an increased current flow, respectively. Regarding the addressing of such storage cells equipped with the bipolar transistors it is furthermore highly desirable to have circuit properties available for the writing and reading process which are of a maximum symmetry, or which are equal, respectively. In the cases of where diodes or transistors are used for the coupling of the cells to the bit line there exists, owing to this respective asymmetrical conduction properties considerable differences for the writing and reading process which result e.g. in relatively high writing currents.